MT48V4M32LFFF View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT48V4M32LFFF

SYNCHRONOUS DRAM

Micron Technology 

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ADVANCE

128Mb: x16, x32

MOBILE SDRAM

INITIALIZE AND LOAD MODE REGISTER1,2

CLK

CKE

COMMAND5

DQML, DQMU

A0-A9, A11

A10

BA0, BA1

DQ

T0

((

))

((

))

tCKS tCKH

((

))

((

))

tCMS tCMH

((

))

((

NOP

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

T = 100µs

High-Z

Power-up:

VDD and

CLK stable

T1

((

))

((

tCK ) )

T3

((

))

((

))

T5

((

))

((

))

T7

((

))

((

))

((

((

((

((

))

))

))

))

((

((

((

((

))

))

))

))

((

((

((

((

PRE

))

((

LMR4

))

((

LMR4

))

((

PRE3

))

((

))

))

))

))

((

((

((

((

))

))

))

))

((

((

((

((

))

))

))

))

tAS tAH

((

((

((

((

))

))

))

))

((

CODE

((

CODE

((

((

))

))

))

))

ALL BANKS ( (

((

))

))

((

CODE

((

))

))

tAS tAH

tAS tAH

((

((

) ) BA0 = L, ) )

((

BA1 = H ( (

))

))

CODE

BA0 = L,

BA1 = L

( ( ALL BANKS ( (

))

))

((

((

))

))

tAS tAH

((

((

))

))

((

((

))

))

((

((

((

((

))

))

))

))

tRP

tMRD

tMRD

tRP

Load Extended Load Mode

Mode Register

Register

T9

((

))

((

))

((

))

((

))

((

AR4

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

tRFC

T19

T29

((

))

((

))

((

))

((

))

((

AR4

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

ACT4

RA

RA

BA

tRFC

DON’T CARE

NOTE:

1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.

2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,

BA = Bank Address

3. Optional refresh command.

4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command.

5. Device timing is -10 with 100 MHz clock.

TIMING PARAMETERS

SYMBOL*

tAH

tAS

tCH

tCL

tCK (3)

tCK (2)

tCK (1)

-8

MIN MAX

1

2.5

3

3

8

10

20

-10

MIN MAX

1

2.5

3

3

10

12

25

UNITS

ns

ns

ns

ns

ns

ns

ns

*CAS latency indicated in parentheses.

SYMBOL*

tCKH

tCKS

tCMH

tCMS

tMRD3

tRFC

tRP

-8

MIN MAX

1

2.5

1

2.5

2

80

20

-10

MIN MAX

1

2.5

1

2.5

2

100

20

UNITS

ns

ns

ns

ns

tCK

ns

ns

128Mb: x16, x32 Mobile SDRAM

MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02

40

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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