RAS#
V
V
IH
IL
CASL#/CASH# VVIIHL
ADDR
V IH
V IL
WE#
V IH
V IL
DQ
V IOH
V IOL
OE#
V IH
V IL
16Mb: 1 MEG x16
EDO DRAM
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRWC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS, tCLCH
tASR
tAR
tRAD
tRAH
ROW
tASC
tCAH
COLUMN
tRCS
tRWD
tCWD
tAWD
tACH
tCWL
tRWL
tWP
ROW
tCLZ
OPEN
tAA
tRAC
tCAC
tOE
tDS
tDH
VALID D OUT
tOD
VALID D IN
tOEH
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tAA
tACH
tAR
tASC
tAWD
tASR
tCAC
tCAH
tCAS
tCLCH
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
-5
MIN
MAX
25
12
38
0
42
0
13
8
8
10,000
5
0
5
38
28
8
8
-6
MIN
MAX
30
15
45
0
49
0
15
10
10
10,000
5
0
5
45
35
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tDS
tOD
tOE
tOEH
tRAC
tRAD
tRAH
tRAS
tRCD
tRCS
tRP
tRSH
tRWC
tRWD
tRWL
tWP
-5
MIN
MAX
0
0
12
12
8
50
9
9
50
10,000
11
0
30
13
116
67
13
5
-6
MIN
MAX
0
0
15
15
10
60
12
10
60
10,000
14
0
40
15
140
79
15
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc