MT55L256L36PB-7.5IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT55L256L36PB-7.5IT' PDF : 30 Pages View PDF
1
CLK
CKE#
CE#
ADV/LD#
R/W#
BWx#
ADDRESS
A1
DQ
COMMAND
WRITE
D(A1)
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
2
3
4
5
6
7
8
9
10
A2
READ
Q(A2)
A3
A4
D(A1) Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
Q(A3)
STALL
NOP
A5
D(A4)
READ
Q(A5)
tKHQZ
Q(A5)
tKHQX
DESELECT CONTINUE
DESELECT
DON’T CARE
UNDEFINED
NOP, STALL, AND DESELECT TIMING PARAMETERS
SYM
tKHQX
tKHQZ
-6
MIN MAX
1.5
1.5
3.5
-7.5
MIN MAX
1.5
1.5
3.5
-10
MIN MAX
1.5
1.5
3.5
UNITS
ns
ns
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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