8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL)
X...X00
X...X01
X...X10
X...X11
SECOND ADDRESS (INTERNAL)
X...X01
X...X00
X...X11
X...X10
THIRD ADDRESS (INTERNAL)
X...X10
X...X11
X...X00
X...X01
FOURTH ADDRESS (INTERNAL)
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL)
X...X00
X...X01
X...X10
X...X11
SECOND ADDRESS (INTERNAL)
X...X01
X...X10
X...X11
X...X00
THIRD ADDRESS (INTERNAL)
X...X10
X...X11
X...X00
X...X01
FOURTH ADDRESS (INTERNAL)
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
FUNCTION
READ
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE ABORT/NOP
R/W#
H
L
L
L
L
BWa#
X
L
H
L
H
BWb#
X
H
L
L
H
NOTE: Using R/W# and byte write(s), any one or more bytes may be
written.
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
FUNCTION
READ
WRITE Byte “a”
WRITE Byte “b”
WRITE Byte “c”
WRITE Byte “d”
WRITE All Bytes
WRITE ABORT/NOP
R/W#
H
L
L
L
L
L
L
BWa#
X
L
H
H
H
L
H
BWb#
X
H
L
H
H
L
H
BWc#
X
H
H
L
H
L
H
BWd#
X
H
H
H
L
L
H
NOTE: Using R/W# and byte write(s), any one or more bytes may be written.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
16
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©2001, Micron Technology, Inc.