MT55L512L18PF-7.5IT View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT55L512L18PF-7.5IT' PDF : 30 Pages View PDF
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
STATE DIAGRAM FOR ZBT SRAM
DS
BURST
DS
DS
DESELECT
READ
BEGIN
READ
READ
DS
WRITE
READ
W
RITE
DS
BEGIN
WRITE
WRITE
READ
BURSTWRITE
BURST
BURST
READ
READBURST
WRITE
BURST
WRITE
BURST
KEY:
COMMAND
DS
READ
WRITE
BURST
OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE or
CONTINUE DESELECT
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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