MX29LV004T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A12 to A17 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Address
CE
OE
WE
Data
RY/BY
Erase Command Sequence(last two cycle)
tWC
tAS
2AAh
SA
tAH
tCH
tGHWL
Read Status Data
VA
VA
tWP
tCS
tWPH
tDS tDH
55h
30h
tBUSY
tWHWH2
In
Progress
Complete
tRB
VCC
tVCS
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0732
REV. 1.1, SEP. 19, 2001
31