MX29LV040C
Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Address
CE#
OE#
WE#
Q6/Q2
tRC
VA
tACC
tCE
tCH
tOE
tOEH
tDF
High Z
tOH
Valid Status
(first raed)
VA
VA
VA
Valid Status
(second read)
Valid Data
(stops toggling)
Valid Data
NOTES:
1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
2. CE# must be toggled when toggle bit toggling.
P/N:PM1149
REV. 1.1, AUG. 30, 2005
40