N25Q128A23T12A0F View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

MFG CO.

N25Q128A23T12A0F

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Numonyx -> Micron 

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N25Q128 - 3 V

Volatile and Non Volatile Registers

6.3.2

XIP Volatile Configuration bits (VCR bit 3)

The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to

0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2

or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate

the memory in XIP mode without setting it to 0. See Section 16: Ordering information.

6.4

Volatile Enhanced Configuration Register

The Volatile Enhanced Configuration Register (VECR) affects the memory configuration

after every execution of Write Volatile Enhanced Configuration Register (WRVECR)

instruction: this instruction overwrite the memory configuration set during the POR

sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:

„ enabling of QIO-SPI protocol and DIO-SPI protocol

Warning: WARNING: in case of both QIO-SPI and DIO-SPI enabled, the

memory works in QIO-SPI

„ HOLD (Reset) functionality disabling

„ To enable the VPP functionality in Quad I/O modify operations

„ To define output driver strength (3 bit)

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