NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must
be in high impedance state before Self-Refresh mode is entered).
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with “Input clock frequency change” section.
4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from
subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when
Self Refresh mode was entered. the ODT signal must continuously be registered LOW until tDLLK timings from
subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self
Refresh mode was entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or
after tDLLK).
9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
Fig. 15 DLL Switch Sequence from DLL-on to DLL-off
CK
CK
CMD
1)
CKE
T0
Ta 0
NOP
SRE 2)
ODTLoff
+ 1tck
Ta1
NOP
tCKSRE
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
SRX 5 )
MRS 6)
MRS 7)
MRS 8)
3)
tCKSRX 4)
tXS
tMRD
tMRD
tDLLK
ODT
tCKESR
Th0
Valid
Valid
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting from Idle State.
2) Enter SR.
3) Change Frequency.
4) Clock must be stable at least tCKSRX.
5) Exit SR.
6) Set DLL-on by MR1 A0="0"
7) Start DLL Reset
8) Any valid command
Time
break
Do not
Care
REV 1.2
May. 2011
CONSUMER DRAM
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