NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Write Leveling
For better signal integrity, DDR3/L memory adopted fly by topology for the commands, addresses, control signals, and
clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight
time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS,
tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3/L SDRAM to compensate
the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3/L SDRAM to adjust the DQS -
to CK - relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - to
align the rising edge of DQS -
with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - ,
sampled with the rising edge of DQS - , through the DQ bus. The controller repeatedly delays DQS -
until a
transition from 0 to 1 is detected. The DQS - delay established though this exercise would ensure tDQSS specification.
Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual
tDQSS in the application with an appropriate duty cycle and jitter on the DQS-
signals. Depending on the actual
tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in
“AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is
show as below figure.
Fig. 17: Write Leveling Concept
Source
Diff _ CK
Diff _DQS
Diff _ CK
Destination
Diff _ DQS
DQ
Push DQS to capture
0 -1 transition
DQ
0 or 1
0 or 1
0
1
0
1
DQS/ driven by the controller during leveling mode must be determined by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x8. Therefore, a
separate feedback mechanism should be able for each byte lane. The upper data bits should provide the feedback of the
upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS
(diff_LDQS) to clock relationship.
REV 1.2
May. 2011
CONSUMER DRAM
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