NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Timing details of Write leveling sequence
Fig. 18: DQS -
is capturing CK - low at T1 and CK - & high at T2
CK
CK
CMD
O DT
Di ff_ DQS
On e Pri me DQ:
Prime D Q
Late
Re ma ini ng
DQs
Earl y
Re ma ini ng
DQs
All DQs are Prime :
Late
Re ma ini ng
DQs
Earl y
Re ma ini ng
DQs
M RS
T1
tWLS t WLH
T2
tWLS t WLH
NO P
tMO D
N OP
NO P
tWLDQ SEN
tWLMR D
N OP
t DQSL
NO P
N OP
N OP
tD QS H
tWLO
tDQ SL
t WLO
NO P
N OP
NO P
tD QSH
t WLO
N OP
tW LMRD
tW LO
t WLO
tW LOE
tW LO
tW LOE
tW LO
t WLO
t WLOE
Note:
Undefined
Driving Mode
Time
break
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on
one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state
through out the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode
3. NOP: NOP or deselect
4. diff_DQS is the differential data strobe (DQS,
). Timing reference points are the zero crossings. DQS
is shown with solid line,
is shown with dotted line.
6. DQS/
needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for
regular Writes; the max pulse width is system dependent.
Do not
Care
Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in
undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1).
REV 1.2
May. 2011
CONSUMER DRAM
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