NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Timing detail of Write Leveling exit
Fig. 19: Extended Temperature Usage
CK
CK
CMD
BA
ODT
T0
NOP
T1
T2
NOP
NOP
tWLO
Ta0
Tb0
Tc0
Tc1
NOP
NOP
NOP
NOP
tIS
tODTLoff
tAOFmin
Tc2
MRS
MR1
Td0
NOP
tMRD
Td1
Valid
tMOD
Valid
Te0
NOP
Te1
Valid
Valid
RTT_DQS_DQS
DQS_DQS
RTT _Nom
tAOFmax
DQ
Result = 1
Time Break
Transitioning
Do not Care
Undefined
Driving Mode
Nanya’s DDR3/L SDRAM supports the optional extended temperature range of 0°C toʳ+95°C, TC. Thus, the SRT and ASR
options must be used at a minimum.ʳThe extended temperature range DRAM must be refreshed externally at 2X (double
refresh)ʳanytime the case temperature is above +85°C (and does not exceed +95°C). Theʳexternal refreshing requirement
is accomplished by reducing the refresh period fromʳ64ms to 32ms. However, self refresh mode requires either ASR or
SRT to support theʳextended temperature. Thus either ASR or SRT must be enabled when TC is aboveʳ+85°C or self
refresh cannot be used until the case temperature is at or below +85°C.
Table 14 summarizes the two extended temperature options and Table 15 summarizesʳhow the two extended temperature
options relate to one another
Table 15: Mode Register Description
Field
Bits
Description
Auto Self-Refresh (ASR)
When enabled, DDR3/L SDRAM automatically provides Self-Refresh power management
ASR
MR2(A6)
functions for all supported operating temperature values. If not enabled, the SRT bit must be
programmed to indicate TOPER during subsequent Self-Refresh operation.
0 = Manual SR Reference (SRT)
1 = ASR enable
Self-Refresh Temperature (SRT) Range
SRT
If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh
MR2(A7) operation. If ASR = 1, SRT bit must be set to 0.
0 = Normal operating temperature range
1 = Extended operating temperature range
REV 1.2
May. 2011
CONSUMER DRAM
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