NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Fig. 53: Dynamic ODT: Behavior with ODT pin being asserted together with write
command for the duration of 6 clock cycles.
CK
CK
CM D
A d d ress
ODT
T0
NOP
RTT
D QS/DQ S
DQ
T1
W RS8
V alid
T2
T3
NOP
NOP
O D T L cnw
T4
NOP
T5
NOP
T6
NOP
T7
NOP
T8
NOP
T9
NOP
T10
NOP
T11
NOP
O D TL on
ODTH8
tA O N m in
tA O N m ax
OD TLcw n8
O D TLoff
RTT_W R
tA O Fm in
tA O Fm ax
WL
D in
D in
D in
D in
D in
D in
D in
D in
h
h+1
h+2
h+3
h+4
h+5
h+6
h+7
Do not
care
T ransitioning
Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.
REV 1.2
May. 2011
CONSUMER DRAM
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