Power Integrated Processor for Digital Amplifier
NTP3000
Table 29 Address 0x17: Aout Rising Edge Delay
Bit
7
6
5
4
3
2
Name
ARED
Name
Description
Value
ARED Aout Rising Edge Delay unsigned 0 default
Meaning
1
0
Ref.
Table 30 Address 0x18: Aout Falling Edge Delay
Bit
7
6
5
4
3
2
Name
AFED
Name
Description
Value
AFED Aout Falling Edge Delay unsigned 0 default
Meaning
1
0
Ref.
Table 31 Address 0x19: Bout Rising Edge Delay
Bit
7
6
5
4
3
2
Name
BRED
Name
Description
Value
BRED Bout Rising Edge Delay unsigned 0 default
Meaning
1
0
Ref.
Table 32 Address 0x1A: Bout Falling Edge Delay
Bit
7
6
5
4
3
2
Name
BFED
Name
BFED
Description
Value
Bout falling Edge Delay unsigned 0 default
Meaning
1
0
Ref.
Table 33 Address 0x1B: PWM off & Auto PROTECT Control
Bit
7
6
5
4
3
2
1
Name
1
0
1
0
1
0
APM
Name
POF
APM
Description
PWM off flag
PROTECT flag
Value
0
1
0
1
Meaning
Even if Auto PROTECT condition is met, the
PWM output of all channel is not affected.
When Auto PROTECT condition is met, the
PWM output of all channel goes to the defined
state which is set by the PWM off state control
register (Address 0x03 AHL, BHL).
Even if Auto PROTECT condition is met, the
PROTECT output of all channel is not
affected.
When Auto PROTECT condition is met, the
PROTECT output goes to Low state.
0
POF
Ref.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
25
R0.73-11.2006