NTP3000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'NTP3000' PDF : 37 Pages View PDF
Power Integrated Processor for Digital Amplifier
NTP3000
Table 50 Address 0x60: 3D delay amount
Bit
7
6
5
4
Name
X
X
Name
3D_Delay
Description
3D_Delay
Value
unsigned 1 ~ 40
3
2
3D_Delay
Meaning
1
0
Ref.
Table 51 Address 0x61 3D effect control configuration
Bit
7
6
5
4
Name
X
X
X
X
Name
3BF
Description
3D Bypass Flag
Value
0
1
Bypass
3D on
3
2
X
X
Meaning
1
0
X
3BF
Ref.
Table 52 Address 0x62 PWM Mode Control Register
Bit
7
6
5
4
3
2
1
0
Name
X
X
X
X
X
X
PM
Name
PM
Description
PWM Mode
Value
Meaning
Ref.
00 Forbidden. Must be set as below.
01 1 chip, 2.1 channel mode
10
1 chip 2.0 channel mode or 2.1 channel
with external power stage
Table 52 Address 0x63 Stand-by in 2 Channel mode
Bit
7
6
5
4
3
2
Name
X
X
X
X
X
X
Name
SB
Description
stand-by in
2 Channel mode
Value
0
1
Meaning
Stand-by operation
Normal operation
1
0
X
SB
Ref.
Table 53 Address 0x75: System Status (Read-only)
Bit
7
Name
6
5
FSI
4
3
2
1
MPW LSRC ULCK
Name
ULCK
MPW
PPM
LSRC
Description
sampled PLL
unlock error
MCK/WCK
ratio error
Permanent
PROTECT
Indication flag
ASRC lock status
Value
0
1
0
1
0
1
0
Meaning
PLL is locked state.
PLL is unlocked state.
Ratio is incorrect.
Ratio is correct.
Indicated that PROTECT is in Permanent LOW
state
ASRC is unlocked state.
0
PPM
Ref.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
30
R0.73-11.2006
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