P2V28S20ATP-7 View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'P2V28S20ATP-7' PDF : 51 Pages View PDF
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data
to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQM
DQ
ACT
Xa
0
00
Write
Ya
0
00
PRE
ACT
tRP
Xa
0
0
00
00
tWR
Da 0 Da 1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the
bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
CLK
Command
A0-9,11
A10
BA0-1
DQ
ACT
Write
TBST
Write
Xa
Ya
Yb
0
0
0
00
00
00
Da 0 Da 1
Db 0 Db 1 Db 2 Db 3
JULY.2000
Page-24
Rev.2.2
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