P4C174-8PC View Datasheet(PDF) - Semiconductor Corporation
Part Name
Description
MFG CO.
'P4C174-8PC' PDF : 12 Pages View PDF
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(2)
READ CYCLE NO. 3 (CE CONTROLLED)(2, 3)
P4C174
Notes:
1. Transition is measured ±200 mV from steady state voltage with
Output
Load B. This parameter is sampled, not 100% tested.
2. CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must
be HIGH during address transitions.
3. All address lines are valid no later than the transition of CE to LOW.
4. READ cycle time is measured from the last valid address to the first
transitioning address.
5. Powerup occurs as a result of any of the following conditions:
a) Falling edge of CE.
b) Falling edge of WE (CE active).
c) Any address line transition (CE active).
d) Any Data line transition (CE and WE active).
This device automatically powers down after TPUPD has elapsed from
any of the prior conditions. Power dissipation is therefore a function
of cycle rate, not CE pulse width.
6. CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH
during address transitions.
7. WRITE cycle time is measured from the last valid address to the first
transitioning address.
8. OE is LOW for this WRITE cycle to show TWZ and TOW.
Document # SRAM118 REV C
Page 5 of 12
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