P8XCL580HFT View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'P8XCL580HFT' PDF : 80 Pages View PDF
Philips Semiconductors
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
Product specification
P80CL580; P83CL580
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IIL
input current logic 0
IITL
input current logic 0; HIGH-to-LOW
transition
RRST
RST pull-down resistor
Analog inputs (note 7)
VDD = 5 V; VIN = 0.4 V
VDD = 2.5 V; VIN = 0.4 V
VDD = 5 V; VIN = 0.5VDD
VDD = 2.5 V; VIN = 0.5VDD
−
−
−100 µA
−
−
−50 µA
−
−
−1.0 mA
−
−
−500 µA
10
−
200 kΩ
VIN(A)
Vref(p)(A)
Rref
CAIN
Ae
OSe
DLe
Mctc
analog input voltage
reference voltage
resistance between
Vref(p)(A) and VSSA
analog on-chip input capacitance
absolute error (note 8)
zero-offset error (note 9)
differential non-linearity (note 10)
channel-to-channel matching
(note 11)
VSSA −
2.7
−
25
−
−
3
−
−
−
−
−
−
−
−
VDD
mA
VDD
mA
100 kΩ
−
pF
±1
LSB
±1
LSB
±1
LSB
±1⁄2
LSB
Notes to the DC characteristics
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output
voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise
is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW
transitions during bus operations. In the most adverse conditions (capacitive loading > 100 pF), the noise pulse on
the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an
address latch with a Schmitt trigger strobe input.
2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall
below the 0.9VDD specification when the address bits are stabilizing.
3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD.
4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns;
VIL = VSS; VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD.
5. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = VDD;
RST = VSS.
6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage
below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1.
7. VDD = 2.7 to 6 V; VSS = 0 V; VSSA = 0 V; Vref(p)(A) = VDD; Tamb = −40 to +85 °C, unless otherwise specified.
fxtal(min) = 250 kHz.
8. Absolute error: the maximum difference between actual and ideal code transitions. Absolute error accounts for all
deviations of an actual converter from an ideal converter.
9. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code
transition.
10. Differential non-linearity: the difference between the actual and ideal code widths.
11. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken
from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on
sampling basis.
1997 Mar 14
66
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