PC82573LSL8JD View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'PC82573LSL8JD' PDF : 40 Pages View PDF
82573—Datasheet
Figure 2. Minimum Requirements for Power Supply Sequencing
Max Difference
≤ 0.3 V
3.3V
2.5V
1.2V (Core Supply)
Max Difference ≤ 0.3 V
3.3V
2.5V
1.2V (Core Supply)
Max Difference ≤ 0.3 V
Max Difference
≤ 0.3 V
3.3.2.2
3.3.3
Table 6.
• If the 1.2V and 2.5V rails power up before 3.3V, they should never exceed the 3.3V
supply by more than 0.3 V.
• At power down, all three supplies should be turned off simultaneously. If the 3.3V
supply powers down first, the 1.2V and 2.5V supplies must never exceed the 3.3V
supply by more than 0.3 V.
External LVR Power Down Sequencing
There are no specific power down sequencing and tracking requirements for the 82573
silicon. The risk of latch-up or electrical overstress is small since the only charge storing
in decoupling capacitors is left in the system.
Internally Generated Power Delivery
The 82573 has two internal linear voltage regulator controllers. The controllers use
external transistors to generate 2 of the 3 required voltages: 2.5V (nominal) and 1.2V
(nominal). These two voltages are stepped down from a 3.3V source.
3.3V Internal Power Supply Parameters
Parameter
Description
Min
Max
Units
Rise Time
Time from 10% to 90% mark
5
Monotonicity
Voltage dip allowed in ramp
-
Slope
Ramp rate at any given time between
10% and 90%
Min: 0.8*V(min)/Rise time (max)
-
Max: 0.8*V(max)/Rise time (min)
Operational Range
Voltage range for normal operating
conditions
3.0
Ripple1
Maximum voltage ripple (peak to peak)
-
Overshoot
Maximum overshoot allowed
-
Maximum overshoot allowed duration.
Overshoot Settling (At that time delta voltage should be
Time
lower than 5 mV from steady state
-
voltage)
ms
300
mV
1500
mV/ms
3.6
V
100
mV
660
mV
3
ms
1. The peak to peak output rippled is measured at 20 MHz bandwidth within the operational range.
20
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