PC8576C-1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PC8576C-1' PDF : 57 Pages View PDF
NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blink
frequency, this can be done using the mode-set command to set and reset the display
enable bit E at the required rate (see Table 9).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 15.
SDA
SCL
Fig 15. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 16.
SDA
SCL
S
START condition
Fig 16. Definition of START and STOP conditions
SDA
P
STOP condition
SCL
mbc 622
PCF8576C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 22 July 2010
© NXP B.V. 2010. All rights reserved.
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