PCF2127 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2127' PDF : 101 Pages View PDF
NXP Semiconductors
PCF2127
Accurate RTC with integrated quartz crystal for industrial applications
14.2 I2C-bus timing characteristics
Table 93. I2C-bus characteristics
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of VSS to VDD (see Figure 56).
Symbol Parameter
Standard mode
Fast-mode (Fm)
Unit
Min
Max
Min
Max
Pin SCL
fSCL
SCL clock frequency
tLOW
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
Pin SDA/CE
0
100
0
400
kHz
4.7
-
1.3
-
s
4.0
-
0.6
-
s
tSU;DAT
data set-up time
tHD;DAT
data hold time
Pins SCL and SDA/CE
250
-
100
-
ns
0
-
0
-
ns
tBUF
bus free time between a STOP
4.7
-
1.3
-
s
and START condition
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
s
tHD;STA
hold time (repeated) START
4.0
-
0.6
-
s
condition
tSU;STA
set-up time for a repeated START
4.7
-
0.6
-
s
condition
tr
rise time of both SDA and SCL [1][2][3] -
signals
1 000
20 + 0.1Cb 300
ns
tf
fall time of both SDA and SCL
[1][2][3] -
signals
300
20 + 0.1Cb 300
ns
tVD;ACK
data valid acknowledge time
[4] 0.1
3.45
0.1
0.9
s
tVD;DAT
data valid time
[5] 300
-
75
-
ns
tSP
pulse width of spikes that must be
[6] -
suppressed by the input filter
50
-
50
ns
[1] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[2] Cb is the total capacitance of one bus line in pF.
[3] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows
series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the
maximum tf.
[4] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
[5] tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.
[6] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF2127
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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