PCF5001 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'PCF5001' PDF : 44 Pages View PDF
Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
IE
ON
SK
INTERNAL
STATUS
t STP
t STD
t STD
t IEH
t STH
MCD457 - 1
Fig.6 Status change in display pager mode.
IE
SR
t STP t STH
t SPD
t IEH
t STH
MCD458
Fig.7 Status interrogation in display pager mode.
7.4 Decoding of the POCSAG data stream
The POCSAG coded input data stream is first noise filtered
by a digital filter. From the filtered data a sampling clock
synchronous to the data rate is derived. The PCF5001
supports 512 bits/s and 1200 bits/s data rates. This results
in a 512 Hz or 1200 Hz sampling clock frequency,
respectively. Synchronization on the POCSAG code
structure is performed using the improved Philips
ACCESS® algorithm, which employs a state machine with
six internal states.
A data rate of 2400 bits/s is possible if an external clock
generator of 153.6 kHz is connected to X1. The minimum
supply voltage is then −1.8 V.
The receiver enable output is activated a period equal to
tRXON before the input data is actually needed. The
decoder has first to achieve bit and word synchronization
before it can receive calls. The algorithm searches first for
the preamble and then for synchronization codeword
patterns.
1997 Mar 04
12
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