PCF5001 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'PCF5001' PDF : 44 Pages View PDF
Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
handbook, halfpage
tDI1
t TDI
tDI0
MGL100
Fig.21 Data input timing.
13 PROGRAMMING CHARACTERISTICS
VDD = 0 V; VSS = VPG = −5.0 V (see notes 1, 2 and 3); Vref = VSS; pins 2 and 3 open-circuit; Tamb = 25 °C.
Quartz crystal parameters: f = 32768 Hz; RS(max) = 40 kΩ; CL = 12 pF.
Decoder in OFF status.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Programming; see Fig.19
tRES
tPEW
fEW
tEW
tDR
tPCH
tPCL
tPRS
tPSI
tPSO
tPDH
power-up reset pulse width
erase/write time
erase/write frequency
erase/write cycles
data retention time
data clock HIGH time
data clock LOW time
read set-up time
data set-up time on input
data set-up time on output
data hold time
note 4
Tamb = 85 °C
note 4
note 4
note 4
note 4
note 4
note 4
35
10
1.0
1 000
10
65
65
−
35
−
35
−
−
−
−
1.5
2.0
10000 −
−
−
−
−
−
−
−
35
−
−
−
35
−
−
µs
ms
MHz
−
years
µs
µs
µs
µs
µs
µs
Notes
1. VSS = VPG only required during erase/write (tPEW in Fig.19), otherwise VSS(min) = −1.5 V.
2. Maximum voltage for programming (VPG) is −5.5 V.
3. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled.
4. EEPROM programming is also possible at higher frequencies (76.8 kHz or 153.6 kHz). The timings shown then
become proportionally smaller.
1997 Mar 04
34
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