PCF85133 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF85133' PDF : 53 Pages View PDF
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
12. Static characteristics
Table 20. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
Supplies
VDD
supply voltage
VLCD LCD supply voltage
VPOR power-on reset voltage
IDD
supply current
IDD(LCD) LCD supply current
Logic[2]
fclk(ext) = 1536 Hz; see Figure 20
fclk(ext) = 1536 Hz; see Figure 20
1.8
-
5.5
V
2.5
-
6.5
V
1.0
1.3 1.6
V
[1] -
3
6
A
[1] -
22 45
A
VI
input voltage
VIH
HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF
VIL
LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF
VOH
HIGH-level output voltage
VOL
LOW-level output voltage
IOH
HIGH-level output current at pin CLK; VOH = 4.6 V; VDD = 5 V
IOL
LOW-level output current at pins CLK, SYNC; VOL = 0.4 V; VDD = 5 V
IL
leakage current
at pins OSC, CLK, SCL, SDA, A0 to A2, SA0,
FF; VI = VDD or VSS
CI
input capacitance
I2C-bus
VSS 0.5 -
0.7VDD -
VSS
-
0.8VDD -
-
-
1
-
-
-
1
-
[3] -
-
VDD + 0.5 V
VDD
V
0.3VDD V
-
V
0.2VDD V
-
mA
1
mA
+1
A
7
pF
Input on pins SDA and SCL
VI
VIH
VIL
CI
IOL(SDA)
input voltage
HIGH-level input voltage
LOW-level input voltage
input capacitance
LOW-level output current
on pin SDA
VOL = 0.4 V; VDD = 5 V
VSS 0.5 -
0.7VDD -
VSS
-
[3] -
-
3
-
5.5
V
5.5
V
0.3VDD V
7
pF
-
mA
LCD outputs
VO
output voltage variation on pins BP0 to BP3; Cbpl = 35 nF
on pins S0 to S79; Csgm = 5 nF
RO
output resistance
VLCD = 5 V
on pins BP0 to BP3
100
-
100
-
+100
mV
+100
mV
[4] -
1.5 10
k
on pins S0 to S79
[4] -
6.0 13.5
k
[1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2] The I2C-bus interface of PCF85133 is 5 V tolerant.
[3] Not tested, design specification only.
[4] Outputs measured individually and sequentially.
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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