PCF85133U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF85133U/2DA/1' PDF : 53 Pages View PDF
NXP Semiconductors
PCF85133
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Fig 16. Acknowledgement on the I2C-bus
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8.5 I2C-bus controller
The PCF85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF85133 are
the acknowledge signals from the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data, and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF85133. The entire I2C-bus slave address byte is shown in Table 17.
Table 17. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
0
1
1
1
0
0
SA0
R/W
The PCF85133 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCF85133 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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