PCF85133U/2DA/1Z View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF85133U/2DA/1Z' PDF : 53 Pages View PDF
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
• Up to 16 PCF85133s on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the available PCF85133
slave addresses. All PCF85133 with the same SA0 level acknowledge in parallel to the
slave address. All PCF85133 with the alternative SA0 level ignore the whole I2C-bus
transfer.
5:
VODYHDGGUHVV
FRQWUROE\WH
6
6
$
$
&
2
5
6
5$0FRPPDQGE\WH
0
$ 6
%
/
6 3
%
(;$03/(6
D WUDQVPLWWZRE\WHVRI5$0GDWD
6
6 $ $
$
5$0'$7$
$
5$0'$7$
$3
E WUDQVPLWWZRFRPPDQGE\WHV
6
6 $ $
$
&200$1'
$
$
&200$1'
$3
F WUDQVPLWRQHFRPPDQGE\WHDQGWZR5$0GDWHE\WHV
6
6 $ $
$
&200$1'
$
Fig 17. I2C-bus protocol
$
5$0'$7$
$
5$0'$7$
$3
PJO
After acknowledgement, the control byte is sent, defining if the next byte is a RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM or command data (see Figure 18 and Figure 17). In this way it is possible to
configure the device and then fill the display RAM with little overhead.
06%
&2 56
QRWUHOHYDQW
/6%
Fig 18. Control byte format
PJO
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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