PCF8523 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8523' PDF : 74 Pages View PDF
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
8.8 Register Offset
The PCF8523 incorporates an offset register (address 0Eh), which can be used to
implement several functions, like:
• Aging adjustment
• Temperature compensation
• Accuracy tuning
Table 28. Offset - offset register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
MODE
0[1]
offset is made once every two hours
1
offset is made once every minute
6 to 0 OFFSET[6:0]
see Table 29 offset value
[1] Default value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB
introduces an offset of 4.069 ppm. The values of 4.34 ppm and 4.069 ppm are based on a
nominal 32.768 kHz clock. The offset value is coded in two’s complement giving a range
of +63 LSB to 64 LSB.
Table 29. Offset values (in period time, not frequency)
OFFSET[6:0]
Offset value in
decimal
Offset value in ppm
Every two hours
(MODE = 0)
0111111
+63
+273.420
0111110
+62
+269.080
:
:
:
000 0010
+2
+8.680
000 0001
+1
+4.340
000 0000
0[1]
0[1]
1111111
1
4.340
1111110
2
8.680
:
:
:
100 0001
63
273.420
100 0000
64
277.760
Every minute
(MODE = 1)
+256.347
+252.278
:
+8.138
+4.069
0[1]
4.069
8.138
:
256.347
260.416
[1] Default mode.
The correction is made by adding or subtracting clock correction pulses, thereby changing
the period of a single second.
It is possible to monitor when correction pulses are applied. To enable correction interrupt
generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle a
1⁄4096 s pulse is generated on pin INTx. If multiple correction pulses are applied, a 1⁄4096 s
interrupt pulse is generated for each correction pulse applied.
8.8.1 Correction when MODE = 0
The correction is triggered once per two hours and then correction pulses are applied
once per minute until the programmed correction values have been implemented.
PCF8523
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 28 April 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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