PCF85263ATL/A View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF85263ATL/A

Tiny Real-Time Clock/calendar with alarm function, battery switch-over, time stamp input, and I2C-bus

NXP Semiconductors. 

Prev 21 22 23 24 25 26 27 28 29 30 Next

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

Remark: Note that all timings are generated from the 32.768 kHz oscillator and are based

on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency results

in deviation in timings. This is not applicable to interface timing.

The WatchDog counts down from a software-loaded 5-bit binary value, WDR[4:0], in

register WatchDog. Loading the counter with 0 stops the WatchDog. Loading the counter

with a non-0 value starts the counter. Values from 1 to 31 are allowed.

FRXQWGRZQYDOXH:'5  

:DWFK'RJFORFN

FRXQWHU           

:')

,17$RU,17%

:'5FRXQWV

:'5FRXQWV

GXUDWLRQRIILUVW:DWFK'RJSHULRGDIWHUVWDUW

PD\UDQJHIURP:'5WR:'5FRXQWV

DDD

In this example, it is assumed that the WatchDog flag (WDF) is cleared before the next WatchDog

period expires and that the interrupt output is set to pulsed mode.

Fig 14. WatchDog repeat mode

If a new value of WDR[4:0] is written before the end of the current WatchDog period, then

this value takes immediate effect.

When starting the timer for the first time or when reloading WDR[4:0] before the end of the

current period, the first period has an uncertainty of maximum one count. The uncertainty

is a result of loading the WDR[4:0] from the interface clock which is asynchronous from

the WatchDog source clock. Subsequent WatchDog periods do not have such variation.

Reading the WatchDog register returns the current value of the WatchDog counter (see

Figure 14) and not the initial value WDR[4:0]. Since it is not possible to freeze the

WatchDog counter during read back, it is recommended to read the register twice and

check for consistent results.

8.5.1.1 WatchDog repeat mode

In repeat mode, at the end of every WatchDog period, the WatchDog flag (bit WDF in the

Flags register, Section 8.14 on page 57) is set and the counter automatically reloads and

starts the next WatchDog period. An example is given in Figure 14. The asserted bit WDF

can be used to generate an interrupt. Bit WDF can only be cleared by command.

8.5.1.2 WatchDog single shot mode

In single shot mode, at the end of the countdown period, the WatchDog flag (bit WDF in

the Flags register, Section 8.14 on page 57) is set and the counter stops with the value 0.

The WatchDog register must be reloaded to start another WatchDog period.

PCF85263A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4.1 — 27 November 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

27 of 100

Share Link: