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PCF85263ATT/AJ View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
'PCF85263ATT/AJ' PDF : 100 Pages View PDF
NXP Semiconductors
PCF85263A
Tiny RTC with alarm, battery switch-over, and I2C-bus
8.8 Offset register
The PCF85263A incorporates an offset register (address 24h) which can be used to
implement several functions, such as:
Accuracy tuning
Aging adjustment
Temperature compensation
Table 23. Offset - offset register (address 24h) bit description
Bit
Symbol
Value
Description
7 to 0 OFFSET[7:0]
see Table 25 offset value
There are two modes which define the correction period, normal mode and fast mode.
The normal mode is suitable for offset trimming. The fast mode is suitable for dynamic
offset correction e.g. implementing a temperature correction. The fast mode consumes
more current. Offset mode is defined by bit OFFM in the Oscillator register (Section 8.10).
Table 24. OFFM bit - oscillator control register (address 25h)
See Section 8.10 on page 42.
Bit
Symbol
Value
Description
6
OFFM
offset mode bit
0[1]
normal mode: correction is made every 4
hours; 2.170 ppm/step
1
fast mode: correction is made once every 8
minutes;2.0345 ppm/step
[1] Default value.
For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB
introduces an offset of 2.0345 ppm. The offset value is coded in two’s complement giving
a range of +127 LSB to 128 LSB, see Table 25.
Table 25. Offset values
OFFSET[7:0]
Offset value in
decimal
01111111
01111110
:
0000 0010
0000 0001
0000 0000[1]
11111111
11111110
:
1000 0001
1000 0000
[1] Default value.
+127
+126
:
+2
+1
0
1
2
:
127
128
Offset value in ppm
Normal mode
OFFM = 0
+275.590
+273.420
:
+4.340
+2.170
0[1]
2.170
4.340
:
275.590
277.760
Fast mode
OFFM = 1
+258.3815
+256.3470
:
+4.0690
+2.0345
0[1]
2.0345
4.0690
:
258.3815
260.416
PCF85263A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 27 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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