PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
[1] If the on-chip oscillator is used, this input must be connected to VDD1.
[2] If the internal VLCD generation is used, VLCDOUT, VLCDIN, and VLCDSENSE must be connected together.
[3] If an external VLCD is used in the application, then pin VLCDOUT must be left open-circuit, otherwise the chip
will be damaged.
[4] If only the internal Power-On Reset (POR) is used, this input must be connected to VDD1.
[5] VDD1 is for the logic supply, VDD2 and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and
VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2, and VDD3 must be
connected together.
[6] Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes
fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from
the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be
able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK
output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where
the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to
the system SDA line to guarantee a valid LOW level.
[7] If ENR is connected to VSS, Power-On Reset (POR) is disabled; to enable Power-On Reset (POR) ENR
must be connected to VDD1.
[8] In the application, this input must be connected to VSS.
[9] VSS1 and VSS2 must be connected together.
[10] In the application, T2 must be left open-circuit.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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