PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
7.10 Bias voltage generator
The bias voltage generator generates four buffered intermediate bias voltages. This block
contains the generator for the reference voltages and the four buffers. This block can
operate in two voltage ranges:
• Normal mode: 4.0 V to 9.0 V
• Power save mode: 3.0 V to 9.0 V.
7.11 VLCD generator
The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is
programmed by software.
7.12 Reset
The PCF8531 has the possibility of two reset modes: internal Power-On Reset (POR) or
external reset (RES). The reset mode is selected using the ENR signal. After a reset, the
chip has the following state:
• All row and column outputs are set to VSS (display off)
• RAM data is undefined
• Power-down mode
7.13 Power-down
During power-down, all static currents are switched off (no internal oscillator, no timing
and no LCD segment drive system) and all LCD outputs are internally connected to VSS.
The I2C-bus function remains operational.
7.14 Column driver outputs
The LCD drive section includes 128 column outputs (C0 to C127) which must be
connected directly to the LCD. The column output signals are generated in accordance
with the multiplexed row signals and with the data in the display latch. When less than
128 columns are required, the unused column outputs must be left open-circuit.
7.15 Row driver outputs
The LCD drive section includes 34 row outputs (R0 to R33), which must be connected
directly to the LCD. The row output signals are generated in accordance with the selected
LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused
outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is
R0, R2, ..., R1, R3, etc.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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