PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
bank 0
DDRAM
bank 1
bank 2
bank 3
bank 4
bank 5
PCF8531
34 x 128 pixel matrix driver
top of LCD
R0
R8
LCD
R16
R24
R32
R33 (icon row)
Fig 7. DDRAM to display data mapping
mgs468
8.1 Addressing
Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8,
Figure 9 and Figure 10. The display RAM has a matrix of 34 × 128 bits. The columns are
addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to
Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode
(V = 1), the Y address increments after each byte (see Figure 9). After the last Y address
(Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal
addressing mode (V = 0), the X address increments after each byte (see Figure 10). After
the last X address (X = 127), X wraps around to 0 and Y increments to address the next
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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