PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to
address (X = 0 and Y = 0). The Y address 5 is reserved for icon data and is not affected
by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is
written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM.
LSB
MSB
LSB
MSB
LSB
0
MSB
Fig 8. RAM format and addressing
icon data
X address
127
0
1
2
Y address
3
4
5
mgs469
0
5
1
6
2
3
4
0
1
icon data
0
1
2
Y address
638
3
639
4
5
0
X address
127
Fig 9. Sequence of writing data bytes into RAM with vertical addressing (V = 1)
mgs470
0
1
2
128 129 130
256 257 258
384 385 386
512 513 514
0
1
icon data
127
0
255
1
383
2
Y address
511
3
639
4
5
0
X address
127
Fig 10. Sequence of writing data bytes into RAM with horizontal addressing (V = 0)
mgs471
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
19 of 51
Share Link: 
