PCF8532U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8532U/2DA/1' PDF : 44 Pages View PDF
NXP Semiconductors
PCF8532
Universal LCD driver for low multiplex rates
7.15 Blinker
The display blinking capabilities of the PCF8532 are very versatile. The whole display can
blink at frequencies selected by the blink-select command. The blink frequencies are
fractions of the clock frequency. The ratios between the clock and blink frequencies
depend on the blink mode in which the device is operating, see Table 6.
Table 6. Blink frequencies
Assuming that fclk = 1.800 kHz.
Blink mode
Operating mode ratio
off
-
1
f blink
=
-f---c---l-k-
768
2
f blink = 1--f-5--c-3--l-k6--
3
f blink = 3--f-0--c-7--l-k2--
Blink frequency
blinking off
~2.34 Hz
~1.17 Hz
~0.59 Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink selectively by changing the display RAM data at fixed time
intervals.
If the entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 6).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCF8532, the SDA line becomes fully
I2C-bus compatible. Having the acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAACK pin to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the PCF8532 will not be able
to create a valid logic 0 level. By splitting the SDA input from the output the device could
be used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDAACK pin to the system SDA line to guarantee a valid LOW level.
The following definition assumes SDA and SDAACK are connected and refers to the pair
as SDA.
PCF8532_1
Product data sheet
Rev. 1 — 10 February 2009
© NXP B.V. 2009. All rights reserved.
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