PCF8533 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'PCF8533' PDF : 36 Pages View PDF
Philips Semiconductors
Universal LCD driver for low multiplex rates
Product specification
PCF8533
When display data is transmitted to the PCF8533 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode. The data is
stored as it arrives and does not wait for the acknowledge
cycle as with the commands. Depending on the current
mux mode data is stored singularly, in pairs, triplets or
quadruplets. e.g. in 1 : 2 mux mode the RAM data is stored
every second bit. To illustrate the filling order, an example
of a 7-segment numeric display showing all drive modes is
given in Fig.9; the RAM filling organization depicted
applies equally to other LCD types. With reference to
Fig.9, in the static drive mode the eight transmitted data
bits are placed in bit 0 of eight successive display RAM
addresses. In the 1 : 2 multiplex drive mode the eight
transmitted data bits are placed in bits 0 and 1 of four
successive display RAM addresses.
In the 1 : 3 multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
Table 3 LCD frame frequencies
FRAME FREQUENCY
-f-C-2---L4---K-
NOMINAL FRAME
FREQUENCY (Hz)
64
handbook, full pagewidth
display RAM addresses (rows) / segment outputs (S)
01234
75 76 77 78 79
0
display RAM bits
(columns) /
1
backplane outputs
(BP)
2
3
MGL750
Fig.8 Display RAM bit map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
1999 Jul 30
14
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