PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
PCF8536AT/1
NXP Semiconductors.
'PCF8536AT/1' PDF : 74 Pages View PDF
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
Table 29. Reset state
Reset state of configurable bits shown in the command table format for clarity.
Associated command Bits
7
6
5
4
3
2
1
0
PWM-inversion
PWMI = 0
mode-settings
-
-
-
-
BPS = 0 INV = 0 PD = 0 E = 0
oscillator-control
-
-
-
-
-
EFR = 0 COE = 0 OSC = 0
GPO-output-config
-
-
-
-
GPM1[1:0] = 00
GPM0[1:0] = 00
-
-
-
-
GPM3[1:0] = 00
GPM2[1:0] = 00
-
-
-
-
GPM5[1:0] = 00
GPM4[1:0] = 00
set-MUX-mode
-
-
-
-
-
-
M[1:0] = 00
set-bias-mode
-
-
-
-
-
-
B[1:0] = 00
frame-frequency-LCD -
-
-
FD[4:0] = 01110
frame-frequency-PWM -
-
-
-
FP[3:0] = 0111
GPO-static-data
-
-
-
-
-
GPO0 = 0 GPO1 = 0 GPO2 = 0
-
-
-
-
-
GPO3 = 0 GPO4 = 0 GPO5 = 0
load-data-pointer-LCD -
-
DP[5:0] = 000000
load-data-pointer-PWM -
-
-
-
-
PP[2:0] = 000
The first command sent to the device after the power-on event must be the initialize
command (see Section 8.1.1).
After Power-On Reset (POR) and before enabling the display, the RAM content should be
brought to a defined state by writing meaningful content (e.g. a graphic) otherwise
unwanted display artifacts may appear on the display.
8.2.2 RESET pin function
The RESET pin of the PCF8536 will reset all the registers to their default state. The reset
state is given in Table 29. The RAM contents will remain unchanged. After the reset signal
is removed, the PCF8536 will behave in the same manner as after Power-On Reset
(POR). See Section 8.2.1 for details.
8.2.3 Recommended start-up sequences
This chapter describes how to proceed with the initialization of the chip in different
application modes.
In general, the sequence should always be:
1. Power-on the device,
2. set the display and functional modes,
3. fill the display memory and then
4. turn on the display.
PCF8536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 October 2011
© NXP B.V. 2011. All rights reserved.
22 of 74
Share Link: 