PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

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NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

VDD

R=

tr

2Cb

HOST

PROCESSOR/

MICRO-

CONTROLLER

VDD

SDA

SCL

PCF8536AT

40 to 44 segment

drives

4 to 8 backplanes

LCD PANEL

(up to 320

elements)

A0

VSS

VSS

Fig 12. Typical system configuration for the I2C-bus

013aaa450

VDD

HOST

PROCESSOR/

MICRO-

CONTROLLER

VDD

SDI

SCL

PCF8536BT

CE

40 to 44 segment

drives

4 to 8 backplanes

LCD PANEL

(up to 320

elements)

VSS

VSS

013aaa451

Fig 13. Typical system configuration for the SPI-bus

The host microcontroller maintains the two line I2C-bus or a three line SPI-bus

communication channel with the PCF8536. The appropriate biasing voltages for the

multiplexed LCD waveforms are generated internally. The only other connections required

to complete the system are the power supplies (VDD, VSS, VLCD) and the LCD panel

selected for the application.

The minimum recommended values for external capacitors on VDD and VLCD are 100 nF

respectively. Decoupling of VLCD will help to reduce display artifacts. The decoupling

capacitors should be placed close to the IC with short connections to the respective

supply pin and VSS.

8.4 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

set-bias-mode command (see Table 19) and the set-MUX-mode command (see

Table 18).

Fractional LCD biasing voltages are obtained from an internal voltage divider. The biasing

configurations that apply to the preferred modes of operation, together with the biasing

characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in

Table 31.

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

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