PCF8562TT/2 View Datasheet(PDF) - NXP Semiconductors.
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MFG CO.
'PCF8562TT/2' PDF : 36 Pages View PDF
NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as
well).
Table 6. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM Display RAM addresses (columns)/segment outputs (Sn)
bits (rows)/
backplane
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1
a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2
a5 a2 -
b5 b2 -
c5 c2 -
d5 :
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 7.
Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM Display RAM addresses (columns)/segment outputs (Sn)
bits (rows)/
backplane
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)
0
a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :
1
a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :
2
a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :
3
-
-
-
-
-
-
-
-
-
-
:
In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the content of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
PCF8562
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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