NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
8.5 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.
The least significant bit of the slave address that a PCF8562 will respond to is defined by
the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to
a read access.
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCF8562
slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8562s whose SA0 inputs are set to the alternative level.
R/W
slave address
acknowledge
S
S 0 1 1 1 0 0A 0AC
0
COMMAND
acknowledge
A DISPLAY DATA A P
1 byte
Fig 17. I2C-bus protocol
n ≥ 1 byte(s)
n ≥ 0 byte(s)
update data pointers
001aac266
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8562.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 18). The command bytes are also acknowledged by all addressed
PCF8562s on the bus.
MSB
C
Fig 18. Format of command byte
LSB
REST OF OPCODE
msa833
PCF8562
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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