PCF8563BS/4 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8563BS/4' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8563
Real-time clock/calendar
Table 27. Register reset value[1]
Address Register name Bit
7
6
5
4
3
2
1
0
00h
Control_status_1 0
0
0
0
1
0
0
0
01h
Control_status_2 0
0
0
0
0
0
0
0
02h
VL_seconds
1
x
x
x
x
x
x
x
03h
Minutes
x
x
x
x
x
x
x
x
04h
Hours
x
x
x
x
x
x
x
x
05h
Days
x
x
x
x
x
x
x
x
06h
Weekdays
x
x
x
x
x
x
x
x
07h
Century_months x
x
x
x
x
x
x
x
08h
Years
x
x
x
x
x
x
x
x
09h
Minute_alarm
1
x
x
x
x
x
x
x
0Ah
Hour_alarm
1
x
x
x
x
x
x
x
0Bh
Day_alarm
1
x
x
x
x
x
x
x
0Ch
Weekday_alarm 1
x
x
x
x
x
x
x
0Dh
CLKOUT_control 1
x
x
x
x
x
0
0
0Eh
Timer_control
0
x
x
x
x
x
1
1
0Fh
Timer
x
x
x
x
x
x
x
x
[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 13. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
SDA
500 ns
2000 ns
SCL
8 ms
power-on
Fig 13. POR override sequence
override active mgm664
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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