PCF8563BS/4 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8563BS/4' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8563
Real-time clock/calendar
SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
RECEIVER
Fig 16. System configuration
SLAVE
TRANSMITTER
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER
RECEIVER
mba605
9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 17.
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 17. Acknowledgement on the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc602
PCF8563
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 16 June 2011
© NXP B.V. 2011. All rights reserved.
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