Philips Semiconductors
(67 + 1) × 102 pixels matrix LCD driver
7.9 DDRAM addressing
Product specification
PCF8813
handbook, MfulSl pBagewidth
LSB
MSB
LSB
0
icon data
X address
Y address
0
8
10
101
MGU622
MSB
LSB
Fig.4 Sequence of writing data bytes into the RAM.
Data is downloaded in bytes into the RAM matrix of the
PCF8813 as indicated in Fig.4. The display data RAM has
a matrix of 68 by 102 bits. The columns are addressed by
the X address pointer whilst the rows are addressed in
groups of 8 by the Y address pointer. However, there are
only three rows in bank 8 and one row in bank 10. There is
no bank 9. Thus the address ranges are: X = 0 to
101 (1100101) and Y = 0 to 8 and then 10 (1010). The
PCF8813 is limited to 102 columns by 68 rows,
addressing the RAM outside this area is not allowed.
Two different addressing modes are possible; horizontal
addressing and vertical addressing.
In the horizontal addressing mode (V = 0) the X address
increments after each byte. After the last X address
(X = 101), x wraps-around to 0 and Y increments to
address the next row (see Fig.5) until bank 8 is filled. In the
vertical addressing mode (V = 1) the Y address
increments after each byte. After the Y address (Y = 8),
there is Y wraparound to 0 and X increments to address
the next column (see Fig.6). After the very last address
(X = 101 and Y = 8) the address pointers wraparound to
address X = 0 and Y = 0 in both addressing modes.
Addressing in bank 10 is a special case as these RAM
locations are not automatically accessed. Bank 10 is
reserved for icons. Icon locations must be addressed
explicitly by setting the Y address pointer to 10. The
Y address pointer does not auto-increment when the
X address overflows or underflows (it stays in set to
bank 9). Writing icon data is independent of the horizontal
or vertical addressing (V-bit) but is affected by the Mirror X
(MX) and Mirror Y (MY) bits. MX and MY are described in
Sections 7.11 and 7.12.
2004 Mar 05
10