PDM34078SA7TQ View Datasheet(PDF) - Paradigm Technology
Part Name
Description
MFG CO.
PDM34078SA7TQ
Paradigm Technology
'PDM34078SA7TQ' PDF : 14 Pages View PDF
PDM34078
Sleep Mode Timing Diagram
SNOOZE
1
CLK
ADSP
ADSC
2
ZZ
tZZS
tZZREC
3
NOTES: 1. Data retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 100 ns after leaving ZZ state.
4
Sequential Non-burst Read and Write Timing Diagram
5
CLK
ADSP
ADSC
ADDR
A
B
C
D
ADV
CE1
WE
OE
DQ
Q(A)
Q(B)
Q(C)
Q(D)
READS
NOTES:
1. ADSP = high, ADSC = low, ADV = high, CE1 = low.
2. H ≥ VIH, L ≤ VIL.
E
F
G
H
Q(E)
Q(F)
Q(G)
Q(H)
WRITES
6
7
8
9
10
11
12
Rev 1.0 - 5/01/98
13
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