Switching Characteristics, operational timings
Characteristic
CLK low time
CLK high time
Data in setup time
Data in hold time
CLK rising to output delay
L7:0 output delay
HRES low setup time
Output enable time
Output disable time
X15:0 Expansion setup time
X15:0 Expansion hold time
Symbol
Value
Units
Min. Max.
Conditions
tCL
25
10
ns 32-bit multiplexed output
ns 16-bit output
tCH
25
10
ns 32-bit multiplexed output
ns 16-bit output
tDSU
10
ns
tDH
0
ns
tRD
21 ns Increase to 24ns for DELOP output
tLD
20 ns
tRSU
10
ns
tDLZ
15 ns
Measured with a 15kΩ series resistor and 30pF
tDHZ
15 ns
load capacitance
tXSU
5
ns
tXDH
7
ns
CLK
L7:0 LINE STORE OUTPUTS
HRES
OEN
DATA AND FLAG OUTPUTS
PIXEL DATA IN
X15:0 DATA IN
tLD
t RSU
t CH
t CL
VALID
t RD
tDSU
tDH
VALID
tXSU tXDH
VALID
t DHZ
HIGH Z (D15:0 ONLY)
t DLZ
tXSU tXDH
VALID
Fig. 12 Operational timing
VALID
20