PF38F1602CT70 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'PF38F1602CT70' PDF : 75 Pages View PDF
C3 SCSP Flash Memory
Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections
SUBSTRATE
FLASH DIE
SRAM DIE
D3
S-VSS
E4
F-VPP
S-VSSQ
S-VCC
S-VCCQ
F-VSSQ
F-VCC
F-VCCQ
F-VSS
A9
D9
D10
A10
H8
7.4
XX
Substrate connection to package ball
S-X
SRAM die bond pad connection
F-X
Flash die bond pad connection
Notes:
1.
Substrate connections refer to ballout locations shown in Figure 1 “66-Ball SCSP Package Ballout” on
page 8.
2.
0.1µf capacitors should be used with D9, D10, A10and E4.
3.
Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS.
4.
Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while
also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at
the same time. (See Table 2 “Intel® Advanced+ Boot Block SCSP Ball Descriptions” on page 9 for
a summary of recommended operating modes.) Simultaneous operation of the can be summarized
by the following:
• SRAM read/write are during a Flash Program or Erase Operation are allowed.
• Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
26 Aug 2005
44
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Datasheet
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