PI6C103-XXL View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI6C103-XXL' PDF : 12 Pages View PDF
PI6C103
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Minimum and Maximum Expected Capacitive Loads
Clock
Min. Load Max. Load Units
Notes
CPU Clocks (HCLK)
10
20
1 device load, possible 2 loads
PCI Clocks (PCLK)
30
30
pF Meets PCI 2.1 requirements
REF, 48MHz
10
20
1 device load
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
21$+ !
2
CPUCLK
6
PCICLK
2
REF
CL
CL
CL
1 Device load
Meets PCI2.1 Req.
1 Device load
Ordering Information
P/N
PI6C103H
PI6C103-xxL
Description
28-pin SSOP Package
28-pin TSSOP Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
233
PS8315-2 04/08/99
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