PI6C2520 View Datasheet(PDF) - Pericom Semiconductor
Part Name
Description
MFG CO.
'PI6C2520' PDF : 6 Pages View PDF
PI6C2520
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Low-Noise Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Product Features
Low-Noise Phase-Locked Loop Clock Distribution.
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction. The clock outputs track the Clock Input
modulation.
Maximum clock frequency of 125 MHz.
Zero Input-to-Output delay.
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers for
low noise and EMI reduction.
Operates at 3.3V VCC.
Output-to-Output skew less than 200ps.
Package: Plastic 56-pin TSSOP (A).
Product Pin Configuration
Product Description
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL)
clock driver, distributing low-noise clock signals for Networking
Applications. By connecting the feedback FB_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to any clock output will be nearly zero. This zero-delay
feature allows the CLK_IN input clock to be distributed, providing
5 banks of 4 clocks and an extra clock for feedback.
For test purposes, the PLL can be bypassed by strapping AVCC to
ground. The PI6C2520, which allows a Spread Spectrum clock in-
put, operates at 3.3V VCC and provides integrated series-damping
resistors that make it ideal for driving point-to-point loads. Output
signal duty cycles are adjusted to 50 percent, independent of the
duty cycle at the input clock.
Each bank of outputs can be enabled or disabled via the 1G, 2G,
3G, 4G, and 5G control inputs. When the G inputs are high, the
outputs switch in phase and frequency with CLK_IN. When the G
inputs are low, the outputs are disabled to the logic low state.
Block Diagram
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK_IN
AGND
5G
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
VCC
5Y0
5Y1
GND
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13 56-Pin 44
14 A 43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FB_IN
AGND
FB_OUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
VCC
5Y3
5Y2
GND
1G
2G
3G
4G
5G
CLK_IN
PLL
FB_IN
AVCC
4 1Y [0:3]
4 2Y [0:3]
4 3Y [0:3]
4 4Y [0:3]
4 5Y [0:3]
FB_OUT
1
PS8435B 07/25/00
Share Link: 
