PI6C2972FC View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI6C2972FC' PDF : 7 Pages View PDF
PI6C2972
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Low Voltage PLL Clock Driver
Features
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3VVCC
• + 100ps Typical Cycle–to–Cycle Jitter
• Available packaging: 52-pin LQFP
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver
devices targeted for high-performance CISC or RISC processor
based systems. With output frequencies of up to 125 MHz and
skews of 550ps the PI6C2972 are ideally suited for most synchro-
nous systems. The devices offer twelve low skew outputs plus a
feedback and sync output for added flexibility and ease of
system implementation.
The PI6C2972 features an extensive level of frequency program-
mability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of
1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs
can be realized by pulsing low one clock edge prior to the
coincident edges of the Qa and Qc outputs. The Sync output will
indicate when the coincident rising edges of the above relation-
ships will occur. The Power–On Reset ensures proper program-
ming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output
and the other outputs. The internal power–on reset is designed
to provide this function, but with power–up conditions being
dependent, it is difficult to guarantee. All other conditions of the
fsel pins will automatically synchronize during PLL lock acquisi-
tion.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal
pull–up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external
loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with
the capability to drive 50 Ohm transmission lines. For series
terminated lines each PI6C2972 output can drive two 50 Ohm
lines in parallel thus effectively doubling the fanout of the
device.
Pin Configuration - PI6C2972
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
1
PS8590B 08/11/03
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