PI7C7100 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
'PI7C7100' PDF : 132 Pages View PDF
ADVANCE INFORMATION
PI7C7100
3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566
Table 7–5 shows assertion of P_PERR#. This signal is set under the following conditions:
• PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus.
• The parity-error-response bit must be set in the command register of primary interface.
• PI7C7100 detects a data parity error on the primary bus or detects S_PERR# asserted during the completion
phase of a downstream delayed write transaction on the target (secondary) bus.
Table 7–5. Assertion of P_PERR#
P_PERR#
1 (de-asserted)
Transaction
Type
Read
Direction
Downstream
Bus where error was
detected
Primary
Primary/Secondary
parity error response bits
x/x1
1
Read
Downstream
Secondary
x/x
0 (asserted) Read
Upstream
Primary
1/x
1
Read
Upstream
Secondary
x/x
0
Posted write
Downstream
Primary
1/x
1
Posted write
Downstream
Secondary
x/x
1
Posted write
Upstream
Primary
x/x
1
Posted write
Upstream
Secondary
x/x
0
Delayed write
Downstream
Primary
1/x
02
Delayed write
Downstream
Secondary
1/1
1
Delayed write
Upstream
Primary
x/x
1
Delayed write
Upstream
Secondary
x/x
1x =don’t care
2The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
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09/18/00 Rev 1.1
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