PIC10(L)F320/322
2.2.3 DEVICE MEMORY MAPS
The memory maps for PIC10(L)F320/322 are as shown
in Table 2-2.
TABLE 2-2: PIC10(L)F320/322 MEMORY MAP (BANK 0)
INDF(*)
00h
TMR0
01h
PCL
02h
STATUS
03h
FSR
04h
PORTA
05h
TRISA
06h
LATA
07h
ANSELA
08h
WPUA
09h
PCLATH
0Ah
INTCON
0Bh
PIR1
0Ch
PIE1
0Dh
OPTION_REG 0Eh
PCON
0Fh
OSCCON 10h
TMR2
11h
PR2
12h
T2CON
13h
PWM1DCL 14h
PWM1DCH 15h
PWM1CON 16h
PWM2DCL 17h
PWM2DCH 18h
PWM2CON 19h
IOCAP
1Ah
IOCAN
1Bh
IOCAF
1Ch
FVRCON 1Dh
ADRES
1Eh
ADCON
1Fh
PMADRL
20h
PMADRH
21h
PMDATL
22h
PMDATH
23h
PMCON1
24h
PMCON2
25h
CLKRCON 26h
NCO1ACCL 27h
NCO1ACCH 28h
NCO1ACCU 29h
NCO1INCL 2Ah
NCO1INCH 2Bh
Reserved
2Ch
NCO1CON 2Dh
NCO1CLK 2Eh
Reserved
2Fh
WDTCON 30h
CLC1CON 31h
CLC1SEL1 32h
CLC1SEL2 33h
CLC1POL 34h
CLC1GLS0 35h
CLC1GLS1 36h
CLC1GLS2 37h
CLC1GLS3 38h
CWG1CON0 39h
CWG1CON1 3Ah
CWG1CON2 3Bh
CWG1DBR 3Ch
CWG1DBF 3Dh
VREGCON 3Eh
BORCON
3Fh
40h
General
Purpose
Registers
32 Bytes
5Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
* = Not a physical register.
60h
General
Purpose
Registers
32 Bytes
7Fh
DS40001585D-page 14
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